1. Field of the Invention
The present invention relates, in general, to a printed circuit board (PCB) including an embedded capacitor and a method of fabricating the same and, more particularly, to a PCB including an embedded capacitor, in which the long embedded capacitor is formed through an insulating layer, having a high capacitance and various capacitance designs possible, and a method of fabricating the same.
2. Description of the Prior Art
Recently, high integration and high speed of a semiconductor system has been realized, and thus, the operational speed and performance of a system that includes a semiconductor chip depends on components outside the semiconductor chip as well as those inside the semiconductor chip. Therefore, it is important to assure signal integrity inside and outside the semiconductor chip during the design process.
Furthermore, high speed switching of the semiconductor chip and high frequency signal transmission in electronic systems causes noise due to electromagnetic interference. Particularly, cross talk noise and simultaneous switching noise between adjacent wires and input and output pins serve to reduce signal integrity in the course of designing a high density circuit.
Accordingly, there remains a need to overcome problems with respect to power use, ground bouncing, and power bouncing when many semiconductor chips are mounted on highly dense circuits on PCBs. Hence, the roles of decoupling capacitors and bypass capacitors are very important.
However, in a conventional passive component, resonance occurs within a range of undesired frequency band because of inductance due to a lead line. Hence, embedding the passive component into the PCB is suggested in order to avoid the above problems in a high density mounting technology regarding the PCB.
Generally, discrete chip resistors or discrete chip capacitors have frequently been mounted on most PCBs, but recently, PCBs, in which resistors or capacitors are embedded, are developing.
An embedded PCB has a structure in which the capacitor is mounted on the surface of PCBs or embedded inside PCBs, and if the capacitor is integrated with the PCB to act as one part of the PCB regardless of the size of the PCB, the capacitor is called an “embedded (buried) capacitor” and the resulting PCB is called “printed circuit board including embedded capacitor”.
Typically, the technology of fabricating a PCB including a capacitor embedded therein may be classified into four methods.
Firstly, there is a method of fabricating a polymer thick film type of capacitor, in which the application of a polymer capacitor paste and thermal hardening, that is, drying, are conducted to fabricate a capacitor. In the above method, after the polymer capacitor paste is applied on an internal layer of a PCB and dried, a copper paste is printed on the resulting PCB and dried so that electrodes are formed, thereby making an embedded capacitor.
A second method is to apply a ceramic filled photosensitive resin on a PCB to fabricate a discrete type of embedded capacitor. Motorola Inc. in USA holds a patent for related technologies. In detail, the photosensitive resin containing ceramic powder is applied on the PCB, a copper foil is laminated on the resulting PCB to form upper and lower electrodes, a circuit pattern is formed, and the photosensitive resin is etched to fabricate the discrete type of capacitor.
A third method is to insert an additional dielectric layer having a capacitive characteristic in an internal layer of a PCB so as to substitute for a decoupling capacitor conventionally mounted on a surface of a PCB, thereby fabricating a capacitor. Sanmina Corp. in USA holds a patent for related technologies. According to the third method, the dielectric layer including a power supply electrode and a grounded electrode is inserted into the internal layer of the PCB to fabricate a power distribution type of decoupling capacitor.
A fourth method relates to a PCB including an embedded capacitor, in which a high dielectric polymer capacitor paste that is made of a compound of BaTiO3 and an epoxy resin is packed in an internal layer via hole through the PCB, and a method of fabricating the same. Samsung Electro-Mechanics Corp. in Korea holds a patent for this method. In the fourth method, the via hole is formed through the PCB, and the method comprises 8 steps, which range from a step of forming a plurality of internal layer via holes through a predetermined portion of a copper clad laminate to a step of plating an external layer via hole and a wall of a through hole.
FIGS. 1a to 1n are sectional views illustrating a conventional procedure of fabricating a PCB including an embedded capacitor.
As shown in FIG. 1a, a copper clad laminate, in which a first copper foil layer 12 is formed on an insulating layer 11, is prepared.
As shown in FIG. 1b, a photosensitive dielectric material 13 is layered on the first copper foil layer 12.
As shown in FIG. 1c, a second copper foil layer 14 is laminated on the photosensitive dielectric material 13.
As shown in FIG. 1d, a photosensitive film 20a is laminated on the second copper foil layer 14.
As shown in FIG. 1e, a photo-mask 30a, on which a predetermined capacitor pattern is formed, is closely adhered to the photosensitive film 20a, and subsequently irradiated with ultraviolet rays 40a. At this stage, ultraviolet rays 40a penetrate an unprinted portion 31a of the photo-mask 30a to form a hardened portion 21a of the photosensitive film 20a under the photo-mask 30a. Ultraviolet rays 40a do not penetrate a black printed portion 32a of the photo-mask 30a, thus an unhardened portion 22a of the photosensitive film 20a remains under the photo-mask 30a. 
As shown in FIG. 1f, after the photo-mask 30a is removed, a development process is conducted to remove the unhardened portion 22a of the photosensitive film 20a while only the hardened portion 21a of the photosensitive film 20a remains.
As shown in FIG. 1g, the second copper foil layer 14 is etched using the hardened portion 21a of the photosensitive film 20a as an etching resist, thereby forming an upper electrode layer 14a of an embedded capacitor thereon.
As shown in FIG. 1h, after the hardened portion 21a of the photosensitive film 20a is removed, ultraviolet rays 40b are radiated onto the photosensitive dielectric material 13 using the upper electrode layer 14a as a mask. At this stage, a portion of the photosensitive dielectric material 13, on which the upper electrode layer 14a is not formed, absorbs ultraviolet rays 40b to form a reacted portion 13b, which is capable of being decomposed during a development process using a special solvent (for example, GBL (gamma-butyrolactone)). The other portion of the photosensitive dielectric material 13, on which the upper electrode layer 14a is formed, does not absorb ultraviolet rays 40b, resulting in the persistence of an unreacted portion 13a. 
As shown in FIG. 1i, the development process is conducted to remove the portion 13b of the photosensitive dielectric material 13 that reacted due to the ultraviolet rays, thereby forming a dielectric layer 13a of the embedded capacitor on the photosensitive dielectric material 13.
As shown in FIG. 1j, a photosensitive resin 20b is layered on the first copper foil layer 12, the dielectric layer 13a, and the upper electrode layer 14a. 
As shown in FIG. 1k, a photo-mask 30b, on which a predetermined circuit pattern is formed, is closely adhered to the photosensitive resin 20b, and then irradiated with ultraviolet rays 40c. At this stage, ultraviolet rays 40c penetrate an unprinted portion 31b of the photo-mask 30b to form a hardened portion 21b of the photosensitive resin 20b under the photo-mask 30b. Ultraviolet rays 40c do not penetrate a black printed portion 32b of the photo-mask 30b, thus an unhardened portion 22b of the photosensitive resin 20b remains under the photo-mask 30b. 
As shown in FIG. 11, after the photo-mask 30b is removed, a development process is conducted to remove the unhardened portion 22b of the photosensitive resin 20b while only the hardened portion 21b of the photosensitive resin 20b remains.
As shown in FIG. 1m, the first copper foil layer 12 is etched using the hardened portion 21b of the photosensitive resin 20b as an etching resist, thereby forming a lower electrode layer 12a and the circuit pattern 12b of the embedded capacitor thereon.
As shown in FIG. 1n, the hardened portion 21b of the photosensitive resin 20b is removed. After an insulating layer is laminated, circuit pattern formation, solder resist formation, nickel/gold plating, and external structure formation processes are implemented, thereby creating the PCB 10 including the embedded capacitor.
The conventional procedure of fabricating the PCB 10 including the embedded capacitor is schematically disclosed in U.S. Pat. No. 6,349,456 assigned to Motorola Inc. in USA.
Meanwhile, recently, an increase in a self resonance frequency (SRF) of a passive component, such as a capacitor, which is mounted on a PCB, is required according to a frequency increase needed in a high-frequency system. Furthermore, in a decoupling capacitor used to stabilize a power source, it is necessary to reduce impedance at a high frequency.
To improve the SRF of the capacitor and reduce impedance at the high frequency, demand for an embedded capacitor, which is capable of reducing parasitic inductance in a capacitor, is growing. In PCB design, since the integration of circuit patterns continuously increases, circuit patterns must be made fine.
However, in the conventional PCB 10 including the embedded capacitor, as shown in FIG. 1k, surface level variation occurs between the photo-mask 30b and the photosensitive resin 20b during an exposure process, causing diffraction of ultraviolet rays 40c at a corner of the black printed portion 32b of the photo-mask 30b. Thus, as shown in FIG. 11, the conventional PCB has an undesirable lower limit to the width of a pattern of the photosensitive resin 20b. 
Additionally, as shown in FIG. 1j, in the conventional PCB 10 including the embedded capacitor, the photosensitive resin 20b must be applied on a wall of the dielectric layer 13a so as to protect the dielectric layer 13a during a process of etching the first copper foil layer to form the lower electrode layer 12a and the circuit pattern 12b. Accordingly, as shown in FIG. 1n, a portion of the lower electrode layer 12a unnecessarily protrudes from the upper electrode layer 14a and the dielectric layer 13a. 
The protrusion of the lower electrode layer 12a acts as a conductor in a high frequency environment, causing parasitic inductance, resulting in poor electric performance of electronic goods.
As well, the conventional PCB 10 including the embedded capacitor is problematic in that since the electrode layers 12a, 14a are formed on the upper and lower sides of the PCB, integration of the embedded capacitor is poor, thus limiting an increase of capacitance.